As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems employ memories to store instructions and data. From time to time, certain portions of such memories may acquire a defect, making such portions unusable. Traditionally, the occurrence of such defects required replacement of such memory, which may be costly in terms of labor and hardware, as well as system downtime. More recent approaches to such failures and defects have included the use of error correction code (ECC) memory which requires significant logic and/or software complexity and significant cost to add the extra parity bit component and register.
Further, up to 8% or more of dynamic random access memory (DRAM) modules are affected by single bit failures. As DRAM sizes grow, the need to provide a methodology for repairing marginally faulty cells in non-error correcting code (non-ECC) memory based platforms continues to increase. Some methods, such as enhanced pre-boot system assessment (ePSA) fault tolerant memory feature, may resolve some faulty cell issues post failure by mapping out failing memory regions of the DRAM. However, memory diagnostics must be ran before failure occurs or data corruption and/or a loss of content may occur. On servers, ECC memory allows single bit correction to be performed in real-time, however on client devices, or traditionally consumer information handling systems, no such capability exists.
Further, row hammer tests require special stress algorithms to identify row to row coupling. Such coupling is identified by constantly toggling one row to see if the data of an adjacent row changes. This constant toggling requires a significant amount of time and is seldom executed to the extent necessary to discover all the problems or issues with the memory. Prior solutions rely on the need for ECC memory or memory testing if performed only after a problem is seen by an end user. For example, in one prior solution ePSA must be ran before any memory fix may be implemented which may result in data corruption as client memory does not have ECC. The present disclosure contemplates executing certain procedures in the background during OS operation such that normally prohibitively long typical factory memory tests may be implemented.